1/6 esda6v1u1 august 2002 - ed: 3a so-8 functional diagram transil array for esd protection application specific discretes a.s.d. benefits high esd protection level : up to 25 kv high integration suitable for high density boards iec61000-4-2 : level 4 mil std 883c-method 3015-6 : class3 (human body model) complies with the following standards : where transient overvoltage protection in esd sensitive equipment is required, such as : n computers n printers n communication systems n gsm handsets and accessories n car radio it is particulary recommended for parallel port protection where the line interface withstands only 2 kv esd surge. applications n 6 unidirectional transil functions n low leakage current: i r max. < 2 m a n 200 w peak pulse power (8/20 m s) features descrition the esda6v1u1 is a monolithic voltage suppressor designed to protect components which are connected to data and transmission lines against esd. it clamps the voltage just above the logic level supply for positive transients, and to a diode drop below ground for negative transients.
esda6v1u1 2/6 symbol parameter v rm stand-off voltage v br breakdown voltage v cl clamping voltage i rm leakage current i pp peak pulse current a t voltage temperature coefficient c capacitance rd dynamic resistance v f forward voltage drop electrical characteristics (t amb =25c) symbol parameter value unit v pp electrostatic discharge mil std 883c - method 3015-6 25 kv p pp peak pulse power (8/20 m s) 200 w t stg t j storage temperature range maximum junction temperature - 55 to + 150 125 c c t l maximum lead temperature for soldering during 10s 260 c absolute maximum ratings (t amb = 25c) types v br @ i r i rm @v rm rd a tcv f @i f min. max. max. typ. max. typ. max. note 1 note 2 0v bias vvma m av w 10 -4 /c pf v ma esda6v1u1 6.1 7.2 1 2 5 0.5 6 100 1.5 200 note 1 : square pulse, ipp = 25a, tp=2.5 m s. note 2 : d v br = a t* (tamb -25c) * v br (25c)
esda6v1u1 3/6 the esda family has been designed to clamp fast spikes like esd. generally the pcb designers need to calculate easily the clamping voltage v cl . this is why we give the dynamic resistance in addition to the classical parameters. the voltage across the protection cell can be calculated with the following formula: v cl =v br +rdi pp where ipp is the peak current through the esda cell. dynamic resistance measurement the short duration of the esd has led us to prefer a more adapted test wave, as below defined, to the classical 8/20 m s and 10/1000 m s surges. 2.5 m s duration measurement wave. as the value of the dynamic resistance remains stable for a surge duration lower than 20 m s, the 2.5 m s rectangular surge is well adapted. in addition both rise and fall times are optimized to avoid any parasitic phenomenon during the measurement of rd. calculation of the clamping voltage use of the dynamic resistance
esda6v1u1 4/6 fig. 1 : peak power dissipation versus initial junction temperature. fig. 3 : clamping voltage versus peak pulse current (tj initial = 25 c). rectangular waveform tp = 2.5 m s. fig. 2 : peak pulse power versus exponential pulse duration (tj initial = 25 c). fig. 5 : relative variation of leakage current versus junction temperature (typical values). fig. 6 : peak forward voltage drop versus peak forward current (typical values). fig. 4 : capacitance versus reverse applied voltage (typical values).
esda6v1u1 5/6 application example : protection of logic-level signals. application example : protection of symmetrical signals. note : capacitance value between any i/o pin and ground is divided by 2.
esda6v1u1 6/6 package mechanical data so-8 plastic packaging : preferred packaging is tape and reel. weight : 0.08g. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written ap- proval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - printed in italy - all rights reserved. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore spain - sweden - switzerland - united kingdom - united states. http://www.st.com marking : logo, date code, e6v1u1 ref. dimensions millimetres inches min. typ. max. min. typ. max. a 1.75 0.069 a1 0.1 0.25 0.004 0.010 a2 1.65 0.065 b 0.35 0.48 0.014 0.019 b1 0.19 0.25 0.007 0.010 c 0.50 0.020 c1 45 (typ) d 4.8 5.0 0.189 0.197 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 f 3.8 4.0 0.15 0.157 l 0.4 1.27 0.016 0.050 m 0.6 0.024 s 8 (max) order code esda 6 v 1 u 1 rl esd array v br min package: so8 plastic unidirectionel packaging: rl = tape and reel = tube
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